A fault tolerant test hardware for L1 cache module in tile CMPs architecture

The present work deals with a fault tolerant approach to design the test structure for detecting the fault of cache in chip multiprocessors (CMPs). Fault detection is simplified using a 2-state 3-neighborhood null boundary cellular automata (CA). This has been elaborated in the earlier work of present authors. Self correcting property, however, has been found only in a 5-neighborhood CA and not in 3-neighborhood CA. This self-correcting or fault tolerant approach is taken as the guideline of the present work to design the fault tolerant test hardware for testing the cache in chip multiprocessors. Following this approach an 83% test accuracy has been achieved in the test hardware.