A 10 Gb/s CDR in SiGe BiCMOS commercial technology with multistandard capability

Author

Centurelli, Francesco ; Golfarelli, Alessandro ; Guinea, Jesus ; Masini, Leonardo ; Morigi, Damiana ; Pozzoni, Massimo ; Scotti, Giuseppe ; Trifiletti, Alessandro

Author_Institution

STMicroelectronics, Cornaredo, Italy

fYear

2003

Firstpage

317

Lastpage

320

Abstract

A 10 Gb/s CDR in SiGe BiCMOS technology featuring multistandard compliance with SDH/SONET and 10 Gb Ethernet specs and generated jitter below 65 mUlpp is presented. The CDR features a 20 mV-sensitivity limiting amplifier, a 2-DFF-based decision circuit to maximize CPM and a dual loop PLL architecture with external reference clock and a novel PD topology. Power consumption is below 780 mW from 2.5 and 3.3 V supplies.

Keywords

BiCMOS integrated circuits; Ge-Si alloys; SONET; decision circuits; mixed analogue-digital integrated circuits; optical fibre LAN; optical receivers; phase detectors; phase locked loops; semiconductor materials; synchronisation; synchronous digital hierarchy; telecommunication standards; 10 Gbit/s; 10Gb Ethernet specification; 2-DFF-based decision circuit; 2.5 V; 3.3 V; 780 mW; SDH/SONET; SiGe; SiGe BiCMOS commercial technology; clock recovery system design; clock/data recovery IC; dual loop PLL architecture; external reference clock; limiting amplifier; monolithic CDR IC; multistandard capability; multistandard compliance; phase detector topology; BiCMOS integrated circuits; Circuit topology; Clocks; Ethernet networks; Germanium silicon alloys; Jitter; Phase locked loops; SONET; Silicon germanium; Synchronous digital hierarchy;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits (RFIC) Symposium, 2003 IEEE

ISSN

1529-2517

Print_ISBN

0-7803-7694-3

Type

conf

DOI

10.1109/RFIC.2003.1213952

Filename

1213952