Parallel two step random walk algorithm to analyze VLSI power grid networks

With the growing complexity of electronics circuits, one of the most critical task for a circuit designer is to design a suitable power distribution network for the desired functioning of electronic circuits. This is accomplished by analyzing power distribution network so that hotspots (lower supply voltages that cause excessive voltage drop) on power rails can be determined efficiently. Usually the size of VLSI power grid network is too big to be analyzed accurately and efficiently on a single computer due to lack of computing resources. Thus, for the efficient and accurate analysis of a power grid network, an appropriate methodology need to be adopted along with the suitable computing environment. In this paper, a method for the efficient analysis of power grid network (in terms of performance only) is proposed which is based on parallel random walk algorithm designed for many-core architectures. This method is 203× faster as compared to the sequential version of the algorithm used for the analysis of randomly generated power grid network of size 25 million nodes with less than 5% error.