Title :
Tiger: a timing-driven gate array and standard cell layout system
Author :
Hong, Xianlong ; Yici Cai ; Qiao, Changge ; Huang, Pujing ; Kang, Zhiwi ; Xue, Tianxiong ; Kuh, Ernest S. ; Cheng, Chung-Kuan
Author_Institution :
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
Abstract :
In this paper, we present Tiger, a fast timing-driven layout system for gate array and standard cell design. It can complete whole layout process from placement to detailed routing. The timing issue is directly formulated and considered at every important stage of Tiger based on RC timing model. Several novel and efficient layout algorithms are used in Tiger. Experiments show that Tiger is much faster than TimberWolf 6.0. It guarantees the chip performance while achieving comparable chip area with TimberWolf
Keywords :
circuit layout CAD; integrated circuit layout; logic CAD; logic arrays; network routing; timing; RC timing model; Tiger; chip area; chip performance; detailed routing; gate array; layout algorithms; placement; standard cells; timing-driven layout system; Capacitance; Delay; Geometry; Performance analysis; Routing; Silicon; Timing; Topology; Wire; Wiring;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 1995 4th International Conference on
Conference_Location :
Beijing
Print_ISBN :
0-7803-3062-5
DOI :
10.1109/ICSICT.1995.500159
