Measurement of de-assertion threshold of power-on-reset circuits

Author

Wadhwa, Sanjay Kumar ; Tripathi, Avinash Chandra

Author_Institution

Freescale Semicond. India Pvt. Ltd., Noida, India

fYear

2015

Firstpage

1

Lastpage

4

Abstract

A test circuit for measuring the de-assertion threshold of a Power-on-Reset (POR) circuit is presented. With the help of the test circuit, POR de-assertion voltage can be measured without requiring a dedicated analog pad or a supply voltage higher than the POR supply voltage. The test circuit does not impact the normal mode of operation of POR and the area and power overhead due to the addition of the test circuit are minimal. The test circuit has been designed and simulated in 28nm CMOS technology. The simulation results show that the maximum error in de-assertion threshold measurement is less than +/- 0.5%.

Keywords

CMOS integrated circuits; integrated circuit testing; CMOS technology; POR deassertion voltage; POR supply voltage; analog pad; complementary metal oxide semiconductor; deassertion threshold measurement; power overhead; power-on-reset circuit; size 28 nm; test circuit; Flip-flops; Fuses; Mathematical model; Power supplies; Semiconductor device measurement; System-on-chip; Voltage measurement; de-assertion threshold; low power analog; power on reset;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design and Test (VDAT), 2015 19th International Symposium on

Conference_Location

Ahmedabad

Print_ISBN

978-1-4799-1742-6

Type

conf

DOI

10.1109/ISVDAT.2015.7208109

Filename

7208109