Title :
An extractor for 3-D parasitic capacitance and resistance
Author :
Yuan, Yanhong ; Wang, Zeyi
Author_Institution :
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
Abstract :
In the development of integrated circuits, parasitic parameters associated with interconnections affect the circuit speeds and functionality greatly in the case of sub-micron process. Many works have been done on the efficient calculation of these parameters. In this paper, a three-dimensional parasitic capacitance extractor is presented. The Boundary Element Method (BEM) is employed to deal with the Laplace´s equation. The simulations and the comparisons showed that the experimental results are excellent agreement with the measured ones, and our extractor is effective in simulation of 3-D parasitic capacitances
Keywords :
Laplace equations; VLSI; boundary-elements methods; circuit analysis computing; digital simulation; integrated circuit interconnections; integrated circuit layout; 3D parasitic capacitance extractor; 3D parasitic resistance extractor; IC design; IC interconnections; Laplace´s equation; boundary element method; circuit simulation; circuit speeds; sub-micron process; Boundary element methods; Capacitance measurement; Computer science; Conductors; Gaussian processes; Integrated circuit interconnections; Integrated circuit technology; Linear systems; Mesh generation; Parasitic capacitance;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 1995 4th International Conference on
Conference_Location :
Beijing
Print_ISBN :
0-7803-3062-5
DOI :
10.1109/ICSICT.1995.500167
