Transient current estimation using S3C (Standard cell current transient characterization)

This paper continues to build on the dynamic current transient estimation method introduced in previous work. Our previously introduced method uses pre-characterized data from standard cells to estimate the total current transient of a path. This method eliminates the necessity of running resource intensive full-chip SPICE simulations to estimate the current transient of a path. Novel contributions of this work include: estimation for multiple overlapping paths, multiple temporally distributed input transition estimation, and estimation for glitches in the logic due to dynamic hazards. Extra characterization points are also introduced which provide a considerably higher accuracy of estimation to SPICE simulations, at the cost of a slightly larger one-time investment during pre-characterization of the standard cell library. Data presented in this paper consists of current estimation of a logic path from the ISCAS-85 C6288 benchmark circuit with very promising results.