TSV aware standard cell placement for 3D ICs

Advantage of 3D ICs is that it has reduced wire-length and greater performance compared to conventional 2D ICs. It is important that a 3D placement tool obtains improved wirelength over 2D placement. In this paper we present the implementation of our 3D placement tool. Our work is based on analytical framework, where we solve nonlinear equations. Placement problem is modeled as quadratic penalty for the density of cells in three dimensions. At first we perform quadratic optimization to obtain an initial placement, followed by solving the objective function using conjugate gradient method. The wire-length obtained by our 3D placement tools show an improvement of 16.4% over the placement tools F3D. In another experiment, where the number of TSVs are determined by initial k-way partitioning of the input netlist, we obtain 52% improvement over F3D, in terms of number of TSVs.