Title :
Programming the Adapteva Epiphany 64-Core Network-on-Chip Coprocessor
Author :
Varghese, Anitha ; Edwards, Ben ; Mitra, Gaurav ; Rendell, Alistair P.
Author_Institution :
Res. Sch. of Comput. Sci., Australian Nat. Univ., Canberra, ACT, Australia
Abstract :
With energy efficiency and power consumption being the primary impediment in the path to exascale systems, low-power high performance embedded systems are of increasing interest. The Parallella System-on-module (SoM) created by Adapteva combines the Epiphany-IV 64-core coprocessor with a host ARM processor housed in a Zynq System-on-chip. The Epiphany integrates low-power RISC cores on a 2D mesh network and promises up to 70 GFLOPS/Watt of processing efficiency. However, with just 32 KB of memory per eCore for storing both data and code, and only low level inter-core communication support, programming the Epiphany system presents several challenges. In this paper we evaluate the performance of the Epiphany system for a variety of basic compute and communication operations. Guided by this data we explore various strategies for implementing stencil based application codes on the Epiphany system. With future systems expected to house 4096 eCores, the merits of the Epiphany architecture as a path to exascale is compared to other competing power efficient systems.
Keywords :
coprocessors; network-on-chip; reduced instruction set computing; 2D mesh network; ARM processor; Adapteva Epiphany 64-core NoC coprocessor; Epiphany architecture; GFLOPS; Parallella system-on-module; Zynq system-on-chip; energy efficiency; exascale system; low-power RISC cores; network-on-chip coprocessor; power consumption; Arrays; Clocks; Coprocessors; Kernel; Programming; Random access memory; Registers; Epiphany; Network-on-chip; Parallella; Stencil;
Conference_Titel :
Parallel & Distributed Processing Symposium Workshops (IPDPSW), 2014 IEEE International
Conference_Location :
Phoenix, AZ
Print_ISBN :
978-1-4799-4117-9
DOI :
10.1109/IPDPSW.2014.112
