• DocumentCode
    1674654
  • Title

    DLL-based clock recovery in a PRML channel

  • Author

    Wang, Ping Ying ; Kao, Hsueh-Wu ; Lin, Yung-Yu ; Yang, Meng-Ta ; Yang, Jin-Bin ; Hsieh, Hsiang Ji ; Cheng, Yuh ; Chen, Chih-Yuan ; Pan, Jyh-Shin

  • Author_Institution
    MediaTek, Hsin-Chu, Taiwan
  • fYear
    2005
  • Firstpage
    570
  • Abstract
    A DLL-based clock recovery circuit is designed to eliminate drawbacks of the VCO while maintaining the advantages of a PLL for frequency multiplication and jitter filtering. This design demonstrates that the tracking jitter is 1/20 of that of a PLL for a 1024 times frequency multiplication. The circuits are verified with PRML detectors for BD/DVD at channel bit rates of 264/478 Mb/s.
  • Keywords
    delay lock loops; digital versatile discs; frequency multipliers; synchronisation; timing jitter; 165 to 496 MHz; 264 to 478 Mbit/s; BD; DLL-based clock recovery; DVD; PRML channel; PRML detectors; channel bit rate; frequency multiplication; jitter filtering; tracking jitter; Circuits; Clocks; DVD; Detectors; Filtering; Frequency conversion; Jitter; Phase locked loops; Time frequency analysis; Voltage-controlled oscillators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    0-7803-8904-2
  • Type

    conf

  • DOI
    10.1109/ISSCC.2005.1494123
  • Filename
    1494123
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1674654