DocumentCode
1674749
Title
GA based diagnostic test pattern generation for transition faults
Author
Bhar, Anupam ; Chattopadhyay, Santanu ; Sengupta, Indranil ; Kapur, Rohit
Author_Institution
Dept. of Electron. & Electr. Commun., Indian Inst. of Technol., Kharagpur, Kharagpur, India
fYear
2015
Firstpage
1
Lastpage
6
Abstract
Accuracy of any diagnosis algorithm depends on the test set used. Test that is able to distinguish more fault pairs is better suited for aiding diagnosis. Standard detection test set is generated to detect faults using less number of test patterns. It is unable to distinguish many fault pairs. To distinguish pairs, more patterns are required that consumes ATE memory and time. In this work we devised an algorithm to generate tests from the detection test itself. The generated tests distinguish transition fault pairs undistinguished by the detection test. Our distinguishing tests are made from the detection test by rearrangement of pseudo-primary and primary input of the two-pattern tests. Additional tester memory is not required for our diagnostic tests.
Keywords
VLSI; automatic test equipment; automatic test pattern generation; fault diagnosis; genetic algorithms; ATE; GA based diagnostic test pattern generation; detection test set; diagnosis algorithm; diagnostic tests; fault detection; transition faults; Circuit faults; Delays; Genetic algorithms; Logic gates; Sociology; Statistics; Test pattern generators; VLSI testing; diagnostic test pattern; fault diagnosis; transition fault;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design and Test (VDAT), 2015 19th International Symposium on
Conference_Location
Ahmedabad
Print_ISBN
978-1-4799-1742-6
Type
conf
DOI
10.1109/ISVDAT.2015.7208122
Filename
7208122
Link To Document