Title :
Low power and hardware cost STUMPS BIST
Author :
Kiran, N. Ravi ; Karthik, A. ; Harish, G. ; Yellampalli, Siva
Author_Institution :
VLSI Dept., VTU Extension Centre UTL Technol. Ltd., Bangalore, India
Abstract :
Traditionally BIST is most widely used testing methodology because of its online and at speed testing capability. The conventional BIST suffers from hardware overhead due to the presence of on-chip test blocks such as TPG, MISR, ROM and ORA. In this paper a low hardware cost BIST is proposed, which eliminates the requirement of external TPG by reconfiguring the first flops of scan chains as TPG and ensures the testability of combinational logic present between flops used for constructing LFSR. The proposed BIST is tested with standard ISCAS´89 benchmark circuits and the experimental results shows that the proposed BIST averagely reduces the area overhead by 25.6 % and power overhead by 22.3 %.
Keywords :
built-in self test; combinational circuits; integrated circuit testing; low-power electronics; shift registers; ISCAS´89 benchmark circuit; LFSR; ORA; ROM; STUMPS BIST; TPG; combinational logic; linear feedback shift register; on-chip test blocks; output response analyzer; self-test using MISR/parallel shift register sequence generator; speed testing; test pattern generator; testing methodology; Benchmark testing; Built-in self-test; Circuit faults; Clocks; Hardware; Very large scale integration; Automatic test equipment (ATE). Circuit Under Test (CUT); Linear Feedback Shift Register (LFSR); Multiple Input Signature Register (MISR); Output response analyzer (ORA) Self-Test Using MISR/Parallel Shift Register Sequence Generator (STUMPS). Test pattern generator (TPG);
Conference_Titel :
VLSI Design and Test (VDAT), 2015 19th International Symposium on
Conference_Location :
Ahmedabad
Print_ISBN :
978-1-4799-1742-6
DOI :
10.1109/ISVDAT.2015.7208125
