A new row decoding architecture for fast wordline charging in NOR type Flash memories

This paper presents a new row decoding architecture implemented in 90nm STM10 triple well CMOS technology for low supply voltage, high speed NOR type Flash memories. The overall design is complemented with a novel stress relaxed high/low or positive/negative level shifter for converting the digital signals operating at 1.2V to higher supply voltages for high voltage applications. The proposed level shifter achieves faster switching speed with low power consumption and less variation with respect to process and temperature.