• DocumentCode
    167510
  • Title

    Exhaustive Key Search on Clusters of GPUs

  • Author

    Barbieri, Davide ; Cardellini, Valeria ; Filippone, Salvatore

  • Author_Institution
    Dipt. di Ing. Civile e Ing. Inf., Univ. di Roma “Tor Vergata”, Rome, Italy
  • fYear
    2014
  • fDate
    19-23 May 2014
  • Firstpage
    1160
  • Lastpage
    1168
  • Abstract
    Exhaustive search is generally a last resort for solving a problem: each possible state of a system is generated and evaluated against a condition to find if the problem solution is attained. In some cases, for example in the reversal of cryptographic hash functions that make use of the salting technique, there are very few valid alternatives. However, the set of candidate solutions can be extremely large and therefore very substantial computing resources are needed to walk through the search space in a reasonable time. On the other hand, exhaustive search is very often embarrassingly parallel and so the task can be easily accelerated by distributing the work on a multitude of devices. In this paper we propose a pattern to parallelize general exhaustive searches on a heterogeneous and hierarchical network of computing nodes. We validate this pattern by applying it to the reversal of MD5 and SHA1 hash functions, both at coarse grain (work dispatching among nodes) and at fine grain (work made by each thread), reaching linear scalability with increasing computing power of the participating nodes. In particular, we show how to implement and optimize the hash key search on a GPGPU, achieving near-maximal throughput on various models of NVIDIA devices programmed with CUDA.
  • Keywords
    cryptography; graphics processing units; parallel architectures; pattern clustering; CUDA; GPU clusters; MD5 hash functions; NVIDIA devices; SHA1 hash functions; cryptographic hash functions; exhaustive key search; hash key search; heterogeneous network; hierarchical network; linear scalability; near-maximal throughput; salting technique; substantial computing resources; Computer architecture; Dispatching; Graphics processing units; Instruction sets; Kernel; Search problems; Throughput; CUDA; brute force search;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel & Distributed Processing Symposium Workshops (IPDPSW), 2014 IEEE International
  • Conference_Location
    Phoenix, AZ
  • Print_ISBN
    978-1-4799-4117-9
  • Type

    conf

  • DOI
    10.1109/IPDPSW.2014.131
  • Filename
    6969513