Fully integrated sigma-delta synthesizer suitable for "indirect VCO modulation" in 2.5G application

A fully integrated ΣΔ fractional synthesizer (included VCO, Loop Filter, Xtal oscillator negative impedance) is implemented in a 0.4 μm, 45 GHz SiGe BiCMOS process. The measured close in phase noise is -106 dBc/Hz at 900 MHz using 26 MHz comparison frequency and frequency resolution less than 5 Hz is achieved. The VCO\´s inductors are not integrated in order to test the PLL performance on different frequency\´s range. Using a 200 kHz close loop bandwidth the level of the tones generated, when critical channels are synthesized, exceed the GSM transmitter specifications without applying any dithering technique. The very low close in phase noise and low level of tone generation, make it suitable for "indirect GMSK VCO modulation" application.