Title :
GM Plan: a gate matrix layout algorithm based on artificial intelligence planning techniques
Author :
Hu, Yu Hen ; Chen, Sao-Jie
Author_Institution :
Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
Abstract :
Gate matrix layout is formulated as a planning problem where a plane (the solution steps) is generated to achieve a goal (the gate matrix layout) that consists of interacting subgoals. Each subgoal corresponds to the placement of a gate to a slot, or to the routing of a net connecting gates. The interaction among subgoals is managed with two artificial-intelligence planning techniques: hierarchical planning and metaplanning. A distance measure is defined and used to arrange the subgoals into prioritized classes in the hierarchical planning phase. Two metaplanning policies-graceful retreat and least impact-are used to decide which subgoal is to be achieved within the same priority class and how it can be achieved. In doing so, GM Plan successfully combines gate placement and net routing of the gate matrix layout into one process and has the potential to deliver better results
Keywords :
CMOS integrated circuits; VLSI; artificial intelligence; circuit layout CAD; logic arrays; CMOS; GM Plan; artificial intelligence planning techniques; distance measure; gate matrix layout algorithm; gate placement; graceful retreat; hierarchical planning; interacting subgoals; interaction among subgoals; least impact; metaplanning; net connecting gates; net routing; prioritized classes; Artificial intelligence; Circuits; Contracts; Greedy algorithms; Joining processes; MOSFETs; Problem-solving; Routing; Strategic planning; Wire;
Conference_Titel :
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location :
Portland, OR
DOI :
10.1109/ISCAS.1989.100732