DocumentCode :
1675334
Title :
A constructive heuristic for application mapping onto an express channel based Network-on-Chip
Author :
D´souza, Sandeep ; Soumya, J. ; Chattopadhyay, Santanu
Author_Institution :
Indian Inst. of Technol. Kharagpur, Kharagpur, India
fYear :
2015
Firstpage :
1
Lastpage :
6
Abstract :
Traditional Mesh based Networks-on-Chips, are inherently slow due to hop-by-hop packet forwarding. The addition of Express Channels has emerged as a viable solution to reduce packet latency. However, there is a lack of application mapping methods, which can take into account the nature of the Express Channels. In this paper a constructive heuristic based approach has been proposed for application mapping onto an Express Channel based Network-on-Chip. The simulation results indicate that the proposed method significantly reduces the average packet delay compared to the existing methods even in the presence of high network load.
Keywords :
heuristic programming; network-on-chip; application mapping methods; average packet delay; constructive heuristic based approach; express channel based network-on-chip; hop-by-hop packet forwarding; mesh based networks-on-chips; packet latency; Delays; Mathematical model; Network topology; Network-on-chip; Runtime; Simulation; Topology; Application Mapping; Express Channels; Network-on-Chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design and Test (VDAT), 2015 19th International Symposium on
Conference_Location :
Ahmedabad
Print_ISBN :
978-1-4799-1742-6
Type :
conf
DOI :
10.1109/ISVDAT.2015.7208147
Filename :
7208147
Link To Document :
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