Design and analysis of on-chip symmetric parallel-plate coupled-line balun for silicon RF integrated circuits

In this paper, we present the design and analysis of an on-chip transformer balun for silicon RFICs. High-performance on-chip transformer baluns for low-noise amplifiers and power amplifiers on multi-layer radio-frequency integrated circuits are constructed. Single-end primary and differential secondary are constructed on different dielectric surface planes. The metal windings of the primary and secondary are in parallel to form coupled lines. Both the primary and the secondary are designed symmetrically for differential operation. Additional layer interfaces and vias are used to provide bridges to assure the geometric symmetry. Examples of designs with test results are discussed.