Particle swarm optimization approach for low temperature BIST

Temperature of a block (a region in the chip) depends on both heat generation (caused by power consumption) and heat dissipation among neighbors. Power aware test solutions targeting low power consumption during testing, may not produce an acceptable thermal aware solution. In this paper, a particle swarm optimization (PSO) based test pattern generation strategy has been proposed for BIST environment such that the peak temperature of the circuit during testing gets minimized. Experimental results of our proposed approach on ISCAS´89 and ITC´99 benchmark circuits show a significant reduction in peak temperature and thermal variance, with either nil or very small compromise in fault coverage.