Designing efficient combinational compression architecture for testing industrial circuits

As scan compression matures, the focus is changing from delivering QoR to other pressing requirements like hierarchical DFT implementation, pin-limited test and enabling high speed shifting of scan chains. Combinational compression schemes have had great success in the last decade in delivering a solution that provided a fast transition from traditional scan based test to compression based test. In this paper, a more efficient combinational test compression technique called zScan is presented. We show that this technology is able to meet tough requirements demanded by todays system-on-a-chip (SoC) designs while delivering competitive test data volume and test application time reduction.