• DocumentCode
    1675632
  • Title

    Development of a solution for achieving known-good-die

  • Author

    Prokopchak, L.

  • Author_Institution
    AEHR Test Syst., Mountain View, CA
  • fYear
    34608
  • Firstpage
    15
  • Lastpage
    21
  • Abstract
    A major problem curtailing the growth of the multichip module market is the IC manufacturer´s inability to provide known-good-die. To address this, a cost-effective process to burn-in and test at the die level is in development
  • Keywords
    integrated circuit testing; multichip modules; ASIC; IC manufacturer; RAM; burn-in; contact resistance; cost-effective process; die level; die substrate alignment; interconnect substrate; known-good-die; Costs; Integrated circuit interconnections; Integrated circuit testing; Manufacturing; Packaging machines; Semiconductor device manufacture; Semiconductor device packaging; Sockets; Substrates; System testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1994. Proceedings., International
  • Conference_Location
    Washington, DC
  • ISSN
    1089-3539
  • Print_ISBN
    0-7803-2103-0
  • Type

    conf

  • DOI
    10.1109/TEST.1994.527931
  • Filename
    527931