Non-ideality analysis of clock-jitter suppressing sampler for wideband ΣΔ analog-to-digital converters

As CMOS processes evolve into smaller and smaller feature sizes, the ability to clock circuits at higher rates and the need of integrating analog and digital systems on a single chip arises. This makes it suitable to use a wideband ΣΔ Analog-to-Digital Converter (ADC), due to its high digital content and robustness against circuit imperfections, as part of a front end for a 3^rd or 4^th generation mobile communications system. One type of ΣΔ that would be appropriate for such an application is suggested by Rusu and Tenhunen (2002). However, wideband operation sets tough jitter constraints on the clock since the oversampling ratio (OSR) is lower than for traditional ΣΔ ADCs. Previously, we have proposed a sampling circuit topology which helps to reduce the effects of non-uniform sampling by averaging. This topology´s jitter suppressing properties are based on certain assumptions which, in reality, are non-ideal. This paper describes an analysis of those non-idealities and their impact on the topology´s jitter suppressing features on a circuit level.