Technology scaling and its side effects

Technology scaling results in reduction of the lateral and vertical dimensions of transistors. The supply voltage (VDD) is scaled down to reduce power dissipation and to maintain device reliability (avoid oxide breakdown). The threshold voltage (Vt) is proportionally scaled down in order to maintain the performance. However, narrow oxide thickness and low Vt result in significant rise in gate leakage and sub-threshold leakage currents, respectively. Therefore, leakage power is now a significant contributor to the total chip power. Hence, both dynamic and leakage power reductions are equally essential for the nanoscale design. Therefore, innovative circuit level techniques must be investigated to reduce both of these power components to extend the battery life for portable applications. Due to aggressive scaling, the number of dopants in the channel of a MOSFET has decreased from 1000´s to a few dozen. Hence, it is impossible to control the number of dopants even in identical adjacent devices, causing random dopant fluctuation (RDF). Towards or beyond the end of technology roadmap, when CMOS scaling will likely become ineffective and/or prohibitively costly, some version(s) of emerging devices will be needed if the industry has to continue to enjoy rapid improvements in performance, lower power dissipation, cost per function, and higher functional density. Recent technology advances such as DG MOSFET (double-gate MOSFET also known as FinFET) and CNFET (Carbon Nanotube Field Effect Transistor) are the promising technologies of choice to replace classical CMOS at the nanoscale level.