Title :
Fast Generation of Large Task Network Mappings
Author :
Berger, K.-E. ; Galea, F. ; Le Cun, B. ; Sirdey, R.
Author_Institution :
Embedded Real Time Syst. Lab., Centre de Saclay, Gif-sur-Yvette, France
Abstract :
In the context of networks of massively parallel execution models, optimizing the locality if inter-process communication is a major performance issue. We propose two heuristics to solve a dataflow process network mapping problem, where a network of communicating tasks is placed into a set of processors with limited resource capacities, while minimizing the overall communication bandwidth between processors. Those approaches are designed to tackle instances of over one hundred thousand tasks in acceptable time.
Keywords :
multiprocessing systems; optimisation; parallel programming; dataflow process network mapping problem; interprocess communication; manycore execution optimization; overall communication bandwidth; parallel execution models; Context; Logic gates; Network topology; Optimization; Partitioning algorithms; Program processors; Topology; heuristics; manycore execution optimization; process network mapping;
Conference_Titel :
Parallel & Distributed Processing Symposium Workshops (IPDPSW), 2014 IEEE International
Conference_Location :
Phoenix, AZ
Print_ISBN :
978-1-4799-4117-9
DOI :
10.1109/IPDPSW.2014.170
