• DocumentCode
    1676781
  • Title

    Parallel processor scheduling for digital signal processing

  • Author

    Kunieda, Hiroaki ; Toyoshima, Shigeru

  • Author_Institution
    Fac. of Eng., Tokyo Inst. of Technol., Japan
  • fYear
    1989
  • Firstpage
    1911
  • Abstract
    The authors study a method for deriving MIMD (multiple-instruction-stream, multiple-data-stream) multiprocessor scheduling with the shortest sampling duration, including processor communication time, for general signal processing algorithms. The method makes use of the repetitive nature of digital signal processing, which reduces the computational complexity of searching for the optimal assignment of operations to processors. The examples show that the proposed algorithm obtains the nearly optimum solution in most cases and works very efficiently
  • Keywords
    digital signal processing chips; parallel processing; scheduling; MIMD multiprocessor scheduling; computational complexity reduction; digital signal processing; general signal processing algorithms; multiple-data-stream; multiple-instruction-stream; optimal assignment of operations; parallel process scheduling; processor communication time; repetitive nature of digital signal processing; search algorithm; shortest sampling duration; Communication networks; Computational complexity; Delay; Digital signal processing; Image processing; Parallel processing; Processor scheduling; Signal processing; Signal processing algorithms; Signal sampling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1989., IEEE International Symposium on
  • Conference_Location
    Portland, OR
  • Type

    conf

  • DOI
    10.1109/ISCAS.1989.100743
  • Filename
    100743