Design of a multi-processor system using TMS320C25 for real time advantage processing

Author

Srinivasan, Sambasiva ; Govindaraj, Harini

Author_Institution

Dept. of Electr. Eng., San Jose State Univ., CA, USA

fYear

1989

Firstpage

1915

Abstract

The design of a system using several TMS320C25 processors for real-time implementation of image processing algorithms is proposed. Different approaches for hardware implementation are examined, and a system based on subframe buffers for each processor is presented. The feasibility of the design is verified by studying an image compression algorithm using two-dimensional cosine transform coding. The algorithm decides the speed of operation and consequently determines the number of processing elements required for real-time implementations. Speeding up of the existing algorithms as well as developing new faster algorithms can simplify the hardware to a large extent

Keywords

computerised picture processing; data compression; multiprocessing systems; real-time systems; TMS320C25; faster algorithms; hardware implementation; image compression algorithm; multi-processor system; processing elements; real time advantage processing; subframe buffers; two-dimensional cosine transform coding; Algorithm design and analysis; Control systems; Digital signal processing; Digital signal processors; Hardware; Image coding; Image processing; Parallel architectures; Real time systems; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1989., IEEE International Symposium on

Conference_Location

Portland, OR

Type

conf

DOI

10.1109/ISCAS.1989.100744

Filename

100744