DocumentCode :
1676906
Title :
Testability features of the MC68060 microprocessor
Author :
Crouch, Alfred L. ; Pressly, Matthew ; Circello, Joe
Author_Institution :
Motorola Inc., Austin, TX, USA
fYear :
34608
Firstpage :
60
Lastpage :
69
Abstract :
This report describes the testability design goals, constraints, and strategies used in the development of the MC68060 microprocessor. It explores the design choices that were made and the considerations that led to those choices. It presents the architectures and methodologies used to implement the design choices, and ends by describing the successes, failures, and future refinements of the test methodologies and architectures
Keywords :
IEEE standards; built-in self test; computer architecture; computer testing; design for testability; integrated circuit testing; logic testing; AC testing; BIST; IEEE 1149.1; MC68060 microprocessor; architectures; embedded cache memories; failures; scan path delay testing; testability design; Clocks; Frequency; Manufacturing; Memory management; Microprocessors; Pipelines; Random access memory; Stress; System buses; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 1994. Proceedings., International
Conference_Location :
Washington, DC
ISSN :
1089-3539
Print_ISBN :
0-7803-2103-0
Type :
conf
DOI :
10.1109/TEST.1994.527936
Filename :
527936
Link To Document :
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