Multi-Way Pipelining for Power-Efficient IP Lookup

Ternary Content Addressable Memories (TCAMs) have been widely adopted for IP lookup engines in today´s routers. However, due to the massive parallelism inherent in their architectures, TCAMs do not scale well in terms of power consumption. On the other hand, SRAM-based pipelined algorithmic solutions become attractive alternatives. This paper proposes a partitioning-based multi-way linear pipeline architecture for power-efficient trie-based IP lookup. We develop a hybrid partitioning scheme to map a routing table onto multiple linear pipelines, ensuring each pipeline uses equal amounts of memory. Within each pipeline, a memory-efficient fine-grained node-to-stage mapping scheme is employed to achieve evenly distributed memory across the stages. Simulation experiments using real-life traces show that our 8-way architecture, storing a backbone routing table with over 200 K prefixes, achieves a 27-fold reduction in power consumption over state-of-the-art TCAM-based solutions, while sustaining a throughput of 590 Gbps for minimum size (40 bytes) packets.