MicroSPARC: a case-study of scan based debug

Author

Holdbrook, Kalon ; Joshi, Sunil ; Mitra, Samir ; Petolino, Joe ; Raman, Renu ; Wong, Michelle

Author_Institution

Sun Microsyst. Inc., Mountain View, CA, USA

fYear

34608

Firstpage

70

Lastpage

75

Abstract

MicroSPARC is a highly integrated, high volume, low-cost CMOS RISC microprocessor. To meet the design goals, it included fully synchronous logic with full testability support, using scannable flops and a JTAG-compliant clock controller. This paper describes the key features of the scan design and how they were used to maximize parallelism in system and tester environments, while reducing bottlenecks in functional and timing debug. The paper concludes with a discussion of lessons learned. A related paper (1994) describes the methodologies used and benefits realized in the tester environment, along with data collected during the debug phase of the project

Keywords

CMOS integrated circuits; boundary scan testing; computer debugging; computer testing; design for testability; integrated circuit testing; parallel architectures; reduced instruction set computing; CMOS RISC microprocessor; JTAG-compliant clock controller; MicroSPARC; bottlenecks; functional debug; parallelism; scan based debug; scannable flops; synchronous logic; testability support; timing debug; CADCAM; Clocks; Computer aided manufacturing; Debugging; Flip-flops; Logic testing; Phased arrays; Prototypes; System testing; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1994. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-2103-0

Type

conf

DOI

10.1109/TEST.1994.527937

Filename

527937