Balancing structured and ad-hoc design for test: testing of the PowerPC 603 microprocessor

Author

Hunter, Craig ; Vida-Torku, E. Kofi ; LeBlanc, Johnny

Author_Institution

Somerset Design Center, Motorola Inc., Austin, TX, USA

fYear

34608

Firstpage

76

Lastpage

83

Abstract

The PowerPC 603 microprocessor is a high performance, low power, and low cost RISC microprocessor which was designed at the Somerset Design Center by a team of Motorola, IBM and Apple engineers. The testability and manufacturability features implemented in the PowerPC 603 microprocessor are presented, as well as the issues involved in reconciling a common test plan for two fabrication facilities with differing expectations

Keywords

boundary scan testing; built-in self test; computer testing; design for testability; integrated circuit testing; logic testing; reduced instruction set computing; Apple engineers; IBM; IEEE boundary scan; Motorola; PLL testing; PowerPC 603 microprocessor; RISC microprocessor; Somerset Design Center; ad-hoc design; functional vector generation; manufacturability; structured design; testability; Circuit testing; Costs; Design engineering; Logic arrays; Logic testing; Manufacturing; Microprocessors; Power engineering and energy; Prefetching; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1994. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-2103-0

Type

conf

DOI

10.1109/TEST.1994.527938

Filename

527938