DocumentCode
1677445
Title
Low Power Approaches to High Speed CMOS Current Steering DACs
Author
Mercer, Douglas A.
Author_Institution
Analog Devices Inc., Wilmington, MA
fYear
2006
Firstpage
153
Lastpage
160
Abstract
This paper discusses a number of circuit approaches which address lowering the power consumed by a modern current steering DAC while maintaining both DC and AC performance levels. An example design provides 14 bit resolution and 250 MSPS conversion rate in a 1P4M 0.18mum CMOS process, with optional 3.3 volt compatible devices. A power dissipation/conversion rate figure of merit of as low as 0.17 mW/MSPS was achieved for 1.8V operation and as low as 0.28 mW/MSPS at 3.3V. SFDR of 70 dB is achieved at a 50 MHz output frequency
Keywords
CMOS integrated circuits; digital-analogue conversion; low-power electronics; 0.18 micron; 1.8 V; 14 bit; 3.3 V; AC performance levels; CMOS process; DC performance levels; high speed CMOS current steering DAC; power conversion rate; power dissipation rate; CMOS analog integrated circuits; CMOS logic circuits; CMOS process; CMOS technology; Current supplies; Frequency; Power dissipation; Switches; USA Councils; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2006. CICC '06. IEEE
Conference_Location
San Jose, CA
Print_ISBN
1-4244-0075-9
Electronic_ISBN
1-4244-0076-7
Type
conf
DOI
10.1109/CICC.2006.320868
Filename
4114930
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