Implications of Proximity Effects for Analog Design

Author

Drennan, P.G. ; Kniffin, M.L. ; Locascio, D.R.

Author_Institution

Freescale Semicond., Inc., Tempe, AZ

fYear

2006

Firstpage

169

Lastpage

176

Abstract

This paper addresses two significant proximity effects, well proximity and STI stress, as they relate to analog circuit design. Device performance is impacted by layout features located near, but not part of the device. This adds new complexities to analog design. In either case, bias points can shift by 20-30%, causing potentially catastrophic failures in circuits. We show, for the first time, that a MOSFET placed close to a well-edge creates a graded channel

Keywords

MOSFET circuits; analogue integrated circuits; integrated circuit design; isolation technology; proximity effect (lithography); MOSFET; STI stress; analog circuit design; catastrophic failures; proximity effects; Analog circuits; CMOS technology; Conductivity; Implants; MOSFET circuits; Mirrors; Protection; Proximity effect; Scattering; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2006. CICC '06. IEEE

Conference_Location

San Jose, CA

Print_ISBN

1-4244-0075-9

Electronic_ISBN

1-4244-0076-7

Type

conf

DOI

10.1109/CICC.2006.320869

Filename

4114933

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1677518