Title :
A Phase-Domain Continuous-Time 2nd-Order ΔΣ Frequency Digitizer
Author :
Sharifkhani, M. ; Sachdev, M.
Author_Institution :
Dept. of ECE, Waterloo Univ., Ont.
Abstract :
A frequency digitizer based on a continuous time delta-sigma PLL is presented. The architecture combines the demodulation and digitization process of a frequency modulated signal. This operation is done at a high IF frequency with an excellent accuracy thanks to the oversampling nature of the loop. Since the digitization occurs in phase domain, the power consumption of the digitizer drops significantly compared to the amplitude domain digitizers operating at the same frequency. In addition, owing to its high dynamic range, the digitizer can easily accommodate the frequency drift and DC offset that exist in the wireless environment. The design is implemented in a 0.18 μm CMOS technology. It operates at 128MHz carrier frequency and consumes 6.5 mW.
Keywords :
CMOS digital integrated circuits; delta-sigma modulation; demodulation; frequency modulation; phase locked loops; 0.18 micron; 128 MHz; 6.5 mW; CMOS technology; continuous time delta-sigma PLL; frequency modulated signal; oversampling loop; phase locked loop; phase-domain continuous-time frequency digitizer; second order delta sigma frequency digitizer; Circuits; Demodulation; Energy consumption; Feedback loop; Frequency conversion; Phase frequency detector; Phase locked loops; Sampling methods; Signal processing; Voltage-controlled oscillators;
Conference_Titel :
Custom Integrated Circuits Conference, 2006. CICC '06. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
1-4244-0075-9
Electronic_ISBN :
1-4244-0076-7
DOI :
10.1109/CICC.2006.320911