Title :
A CMOS 15-Bit 125-MS/s Time-Interleaved ADC with Digital Background Calibration
Author :
Lee, Zwei-Mei ; Wang, Cheng-Yeh ; Wu, Jieh-Tsorng
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsin-Chu
Abstract :
A 15-bit 125-MS/s two-channel time-interleaved pipelined ADC is fabricated in a 0.18 mum CMOS technology, and achieves 91.9 dB SFDR, 69.9 dB SNDR for a 9.99 MHz input. The ADC uses a single sample-and-hold amplifier which employs a precharging circuit technique to mitigate the performance requirements for its opamp. Digital background calibration is applied to maintain the conversion linearity of each A/D channel and also correct both gain and offset mismatches between the two channels. Excluding I/O buffers, the chip occupies an area of 4.3 times 4.3 mm 2 and dissipates 909 mW from a 1.8 V supply
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; calibration; sample and hold circuits; 0.18 micron; 1.8 V; 9.99 MHz; 909 mW; CMOS technology; analog-digital conversion; conversion linearity; digital background calibration; precharging circuit technique; sample-and-hold amplifier; time-interleaved ADC; Analog-digital conversion; BiCMOS integrated circuits; CMOS digital integrated circuits; CMOS technology; Calibration; Choppers; Linearity; MIM capacitors; Pipelines; Sampling methods;
Conference_Titel :
Custom Integrated Circuits Conference, 2006. CICC '06. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
1-4244-0075-9
Electronic_ISBN :
1-4244-0076-7
DOI :
10.1109/CICC.2006.320912
