DocumentCode
1678073
Title
Sequential Circuit Test Generator (STG) benchmark results
Author
Cheng, Wu-tung ; Davidson, Scott
Author_Institution
AT&T Bell Lab., Princeton, NJ, USA
fYear
1989
Firstpage
1939
Abstract
The authors report on the results of running a version of the Sequential Circuit Test Generator (STG3) on the ISCAS-89 sequential circuit benchmarks. First, they present a brief history of STG and briefly describe the algorithms used. They then describe the conditions under which the experiments were run and give the benchmark results. No particular problems were encountered when running STG3 on the benchmark circuits, except for those circuits with many untestable faults. STG3 determines that faults are undetectable fairly quickly, taking only 0.98 s on a totally untestable circuit. The major problem with the circuits considered untestable was in initializing the circuit state
Keywords
fault location; logic testing; sequential circuits; ISCAS-89 sequential circuit benchmarks; Sequential Circuit Test Generator; benchmark results; circuit state; initializing; totally untestable circuit; untestable faults; Algebra; Benchmark testing; Circuit faults; Circuit testing; Clocks; Data structures; Flip-flops; Sequential analysis; Sequential circuits; Sun;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location
Portland, OR
Type
conf
DOI
10.1109/ISCAS.1989.100749
Filename
100749
Link To Document