Title :
A probabilistic neural network hardware system using a learning-parameter parallel architecture
Author :
Aibe, Noriyuki ; Yasunaga, Moritoshi ; Yoshihara, Ikuo ; Kim, Jung H.
Author_Institution :
Master Program of Inf. Sci. & Electron., Univ. of Tsukuba, Japan
fDate :
6/24/1905 12:00:00 AM
Abstract :
A novel PNN (Probabilistic Neural Networks) hardware architecture called ´Sigma Parallel Architecture´ (SPA) is proposed. Different values of the network parameter are calculated in parallel in the SPA and it speeds up the PNN learning as well as recognition overcoming the difficulty in the VLSI implementation. The hardware prototype is developed using FPGA chips and it shows a high speed leaning of about 10 seconds that satisfies the requirements in the real world image recognition tasks
Keywords :
VLSI; field programmable gate arrays; image recognition; neural net architecture; parallel architectures; FPGA chips; Sigma parallel architecture; VLSI; hardware prototype; learning-parameter parallel architecture; network parameter; probabilistic neural network hardware system; real world image recognition tasks; Feedforward neural networks; Image recognition; Kernel; Neural network hardware; Neural networks; Neurons; Parallel architectures; Pattern recognition; Prototypes; Very large scale integration;
Conference_Titel :
Neural Networks, 2002. IJCNN '02. Proceedings of the 2002 International Joint Conference on
Conference_Location :
Honolulu, HI
Print_ISBN :
0-7803-7278-6
DOI :
10.1109/IJCNN.2002.1007495
