Simulation of hierarchical scheduler for ATM switches

Traffic scheduling is an important function that provides service differentiation to a wide range of quality of service (QoS) requirements for connections that belong to different traffic classes. This article presents a simulation based traffic analysis tool for asynchronous transfer mode (ATM) switches. The simulator for the ATM cell scheduler models a complex hierarchical scheduling (HS) discipline with multiple levels of scheduling. The interaction of the first level per virtual circuit (VC) scheduler with second level class scheduler among multiple class types is very complex. It is useful to use the simulator to derive theoretical outcomes of traffic configurations both in live networks and in lab environments. Connection admission control (CAC) algorithms are also incorporated in the simulator for effective bandwidth (EBW) calculation and scheduler weight allocation. Simulation results are presented at the end of the paper.