Two test generation methods for sequential circuits

A description is given of two test generation methods for sequential logic circuits. One method, called the 9ED method, is based on a path sensitization technique and is effective for asynchronous sequential circuits. The other methods, called the 4SP method, is also based on the path sensitization technique and is effective for sequential circuits with a design-for-testability (DFT) structure. The capabilities of these methods are examined with regard to the benchmark circuits prepared for ISCAS´89. The experimental results verified the effectiveness of the 4SP method for these circuits