Title :
A Multi-Standard Low Power 1.5-3.125 Gb/s Serial Transceiver in 90nm CMOS
Author :
Yokoyama-Martin, D.A. ; Krishna, K. ; Stonick, J. ; Caffee, A. ; Gamble, E. Kolet ; Jones, C. ; McNeal, J. ; Parker, J. ; Segelken, R. ; Sonntag, J. ; Umino, K. ; Upton, J. ; Weinlader, D. ; Wolfer, S.
Author_Institution :
Synopsys Inc., Mountain View, CA
Abstract :
A low power, small area transceiver PHY that supports PCIetrade, SATA II, and XAUI was fabricated in TSMC´s 90nm dual gate CMOS. Each lane occupies an area of 400mum times 430mum. Operation also requires a clock module of 400mum times 430mum. A 4-lane, wirebond testchip consumes 195mW of power at 3.125Gb/s. The paper focuses on the analog sections of the transmit and receive blocks
Keywords :
CMOS integrated circuits; low-power electronics; transceivers; 1.2 V; 1.5 to 3.125 Gbit/s; 38.7 to 44 GHz; 45 mW; 90 nm; TSMC; clock module; dual gate CMOS; low power; multi standard; serial transceiver; wirebond testchip; Calibration; Circuit testing; Clocks; Phase locked loops; Physical layer; Protocols; Resistors; Silicon; Transceivers; Transmitters;
Conference_Titel :
Custom Integrated Circuits Conference, 2006. CICC '06. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
1-4244-0075-9
Electronic_ISBN :
1-4244-0076-7
DOI :
10.1109/CICC.2006.320970
