Device Technology for embedded DRAM utilizing stacked MIM(Metal-Insulator-Metal) Capacitor

Author

Yamagata, Y. ; Shirai, H. ; Sugimura, H. ; Arai, S. ; Wake, T. ; Inoue, K. ; Sakoh, T. ; Sakao, M. ; Tanigawa, T.

Author_Institution

Adv. Device Dev. Div., NEC Electron. Corp., Kanagawa

fYear

2006

Firstpage

421

Lastpage

427

Abstract

This paper presents embedded DRAM device technology utilizing stacked MIM(metal-insulator-metal) capacitor. Targeted for high random-access performance as well as low-power data-streaming applications, original structure named "full metal DRAM" has been devised and implemented from 150nm generation. This features reduced parasitic resistance of DRAM cell and fully-compatible CMOS Trs. characteristics with that of leading-edge CMOS. In 90nm generation, ZrO ² is introduced as capacitor dielectric material for cell size reduction. For the next generation of 55nm, high-k gate dielectric(HfSiON) will be introduced in CMOS platform, which can be effectively exploited for embedded DRAM scaling and performance improvement

Keywords

CMOS integrated circuits; DRAM chips; MIM devices; capacitors; hafnium compounds; high-k dielectric thin films; low-power electronics; zirconium compounds; 150 nm; 55 nm; 90 nm; CMOS platform; HfSiON; MIM capacitor; ZrO²; capacitor dielectric material; cell size reduction; device technology; embedded DRAM; high random access performance; high-k gate dielectric; low power data streaming; parasitic resistance; Capacitors; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2006. CICC '06. IEEE

Conference_Location

San Jose, CA

Print_ISBN

1-4244-0075-9

Electronic_ISBN

1-4244-0076-7

Type

conf

DOI

10.1109/CICC.2006.320987

Filename

4114994