Title :
Self-referenced sense amplifier for across-chip-variation immune sensing in high-performance Content-Addressable Memories
Author :
Arsovski, Igor ; Wistort, Reid
Author_Institution :
IBM Silicon Solutions, Essex Junction, VT
Abstract :
A memory sense-amplifier self-calibrates during sense-line precharge to reduce the required signal development and minimize data capture timing uncertainty caused by random device variation. When compared to conventional single-ended sensing, this method reduces sense time by 70% and decreases sense-power by 40%. The self-referenced sensing scheme (SRSS) is used to implement the search operation in content-addressable memory (CAM) testchip. Fabricated in 1V 65nm CMOS, this scheme achieves a 0.6ns search time on a 70bit sense-line while consuming only 0.99 fJ/bit/search. Measured search access time on a five bank 64times240bit ternary CAM including selective precharge is 2.2ns. Measured power consumption at 450MHz is 10mW. Hardware shows robust search operation over a voltage range of 0.6V to 1.7V
Keywords :
CMOS integrated circuits; amplifiers; content-addressable storage; integrated circuit reliability; 0.6 to 1.7 V; 10 mW; 450 MHz; 65 nm; CMOS; across-chip-variation immune sensing; content-addressable memories; random device variation; self-referenced sense amplifier; self-referenced sensing scheme; sense-line precharge; Automatic testing; CADCAM; Computer aided manufacturing; Energy consumption; Hardware; Power measurement; Robustness; Time measurement; Timing; Uncertainty;
Conference_Titel :
Custom Integrated Circuits Conference, 2006. CICC '06. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
1-4244-0075-9
Electronic_ISBN :
1-4244-0076-7
DOI :
10.1109/CICC.2006.320819
