Title :
A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS
Author :
Park, Sunghyun ; Palaskas, Yorgos ; Ravi, Ashoke ; Bishop, Ralph E. ; Flynn, Michael P.
Author_Institution :
Michigan Univ., Ann Arbor, MI
Abstract :
A 5-bit flash ADC incorporates 20 mum by 20 mum inductors to improve both comparator preamplification bandwidth and regeneration speed. A switched-cascode scheme reduces comparator kickback. Offset cancellation is achieved by modifying the comparator reference voltages without degrading high-speed performance. The ADC achieves a measured SNDR of 27.5 dB for a 5 MHz input at 4 GS/s, and 23.6 dB for a 1 GHz input at 3.5 GS/s. The power consumption (including clock buffer and ladder) is 227 mW at 3.5 GS/s. The active area is 0.658 mm2
Keywords :
CMOS integrated circuits; analogue-digital conversion; comparators (circuits); 227 mW; 35 GHz; 5 bit; 7 GHz; 90 nm; CMOS technology; analog-digital convertors; comparator kickback; comparator preamplification bandwidth; offset cancellation; Bandwidth; Circuits; Clocks; Inductance; Inductors; Parasitic capacitance; Sampling methods; Switches; USA Councils; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 2006. CICC '06. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
1-4244-0075-9
Electronic_ISBN :
1-4244-0076-7
DOI :
10.1109/CICC.2006.320890
