A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS

A 5-bit flash ADC incorporates 20 mum by 20 mum inductors to improve both comparator preamplification bandwidth and regeneration speed. A switched-cascode scheme reduces comparator kickback. Offset cancellation is achieved by modifying the comparator reference voltages without degrading high-speed performance. The ADC achieves a measured SNDR of 27.5 dB for a 5 MHz input at 4 GS/s, and 23.6 dB for a 1 GHz input at 3.5 GS/s. The power consumption (including clock buffer and ladder) is 227 mW at 3.5 GS/s. The active area is 0.658 mm²