• DocumentCode
    1679864
  • Title

    Performance analysis of the sliding-window parallel packet switch

  • Author

    Liu, Chia-Lung ; Lin, Woei ; Wu, Chin-Chi

  • Author_Institution
    Dept. of Comput. Sci., Nat. Chung-Hsing Univ., Taichung, Taiwan
  • Volume
    1
  • fYear
    2005
  • Firstpage
    179
  • Abstract
    The paper is concerned with performance analysis of the parallel packet switch (PPS) with sliding window (SW) scheme. The PPS is composed of multiple packet switches operating independently and in parallel. The traditional PPS dispatch algorithm uses round-robin (RR) (Iyer, S., IEEE Trans. Networking, vol.11, no.2, p.314-24, 2003; Aslam, A. and Christensen, K., LCN 2002, p.270-7, 2002). The class of PPS is characterized by the deployment of parallel center-stage switches such that all memory buffers run slower than the external line rate. We propose a new SW packet switching scheme for the PPS, called SW-PPS. The SW-PPS can operate in a pipeline fashion to achieve the overall switching operation. Under Bernoulli data traffic, the SW-PPS provides significantly higher performance when compared with RR-PPS. The paper presents a mathematical analytical model for RR-PPS and SW-PPS.
  • Keywords
    buffer storage; packet switching; telecommunication traffic; Bernoulli data traffic; memory buffers; parallel center-stage switches; pipeline operation; round-robin parallel packet switch; sliding-window parallel packet switch; Analytical models; Computer science; High-speed networks; Multiplexing; Packet switching; Performance analysis; Pipelines; Round robin; Switches; Switching circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Communications, 2005. ICC 2005. 2005 IEEE International Conference on
  • Print_ISBN
    0-7803-8938-7
  • Type

    conf

  • DOI
    10.1109/ICC.2005.1494343
  • Filename
    1494343