Die Stacking Technology for Terabit Chip-to-Chip Communications

In this paper a die stacking technology, leveraging on through die via (TDV) integration and wafer bonding, is presented. Using state-of-the-art volume manufacturing environment, 10:1 aspect ratio TDV and wafer-level bonding technology are developed and initial electrical and reliability characterization results of TDVs are provided. The opportunities for die-stacking technology to alleviate chip-to-chip communication bottleneck are discussed and visions for stacked-die applications, utilizing a programmable virtual backplane, are presented