• DocumentCode
    1680189
  • Title

    Transforming behavioral specifications to facilitate synthesis of testable designs

  • Author

    Dey, Sujit ; Potkonjak, Miodrag

  • Author_Institution
    C&C Res. Labs., NEC Res. Inst., Princeton, NJ, USA
  • fYear
    34608
  • Firstpage
    184
  • Lastpage
    193
  • Abstract
    Recently, several high level synthesis approaches have been proposed to synthesize testable data paths from behavioral specifications. This paper introduces a novel technique to transform behavioral specifications, such that an existing behavioral test synthesis system can generate area-efficient, testable designs with significantly lower partial scan overhead. Experimental results demonstrate the significant savings in partial scan overhead when the transformation is applied before using the behavioral test synthesis system to synthesize 100% test-efficient designs
  • Keywords
    automatic testing; boundary scan testing; built-in self test; high level synthesis; logic testing; area-efficient testable design; behavioral specification; behavioral specifications; behavioral test synthesis; high level synthesis; partial scan overhead; savings; synthesis of testable designs; testable data paths; Automatic test pattern generation; Automatic testing; Circuit synthesis; Circuit testing; Flow graphs; Hardware; High level synthesis; Laboratories; System testing; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1994. Proceedings., International
  • Conference_Location
    Washington, DC
  • ISSN
    1089-3539
  • Print_ISBN
    0-7803-2103-0
  • Type

    conf

  • DOI
    10.1109/TEST.1994.527949
  • Filename
    527949