Title :
A 10Gbps Burst-Mode CDR Circuit in 0.18μm CMOS
Author :
Liang, Che-Fu ; Hwu, Sy-Chyuan ; Liu, Shen-Iuan
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei
Abstract :
A 10Gbps burst-mode clock and data recovery (CDR) circuit has been fabricated in 0.18mum CMOS technology. It recovers the input data and clock within 32 bits by using a gated voltage-controlled oscillator, a quadrature generator and a phase-aligning loop incorporating a half-rate bang-bang phase detector and a digital phase interpolator. The measured peak-to-peak jitter of the recovered clock is 10.44ps. The die area is 1.73 times 2.01 mm2 and draw 200mW from a 1.8V supply.
Keywords :
CMOS digital integrated circuits; clocks; phase detectors; synchronisation; voltage-controlled oscillators; 0.18 micron; 1.8 V; 10 Gbit/s; 10.44 ps; 200 mW; 32 bit; CMOS technology; burst-mode CDR circuit; clock and data recovery circuit; digital phase interpolator; gated voltage-controlled oscillator; half-rate bang-bang phase detector; phase-aligning loop; quadrature generator; CMOS technology; Circuits; Clocks; Detectors; Filters; Jitter; Passive optical networks; Phase detection; Phase locked loops; Voltage-controlled oscillators;
Conference_Titel :
Custom Integrated Circuits Conference, 2006. CICC '06. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
1-4244-0075-9
Electronic_ISBN :
1-4244-0076-7
DOI :
10.1109/CICC.2006.320828
