Low Voltage and Low Power 64-Bit Hybrid Adder Design Based on Radix-4 Prefix Tree Structure

Author

Shao-Hui Shieh ; Der-Chen Huang ; Ying-Yi Chu

Author_Institution

Dept. of Electron. Eng., Nat. Chin-Yi Univ. of Technol., Taichung, Taiwan

fYear

2014

fDate

10-12 June 2014

Firstpage

446

Lastpage

449

Abstract

A 64-bit hybrid adder design is proposed by using both radix-4 prefix tree structure and carry select adder for low voltage and low power applications. In order to optimize the features of this adder, some design issues are concerned including optimal layout for CMOS group generate/propagate circuit to reduce area, design of carry bypass adder (CBA) without conflict to boost speed, carry select adder (CSA) design with speed and area efficiency, and so on. Based on TSMC 90 nm CMOS mixed signal process technology at 1V supply voltage, the experimental results reveal that the proposed 64-bit hybrid adder is superior to other referenced adders, and has 203 ps delay time, 9.58 mw average power, and 96×76 μm² area.

Keywords

CMOS integrated circuits; adders; digital arithmetic; logic design; power aware computing; CBA; CMOS group; CMOS mixed signal process technology; CSA design; TSMC; carry bypass adder; low power 64-Bit hybrid adder design; low voltage 64-Bit hybrid adder design; radix-4 prefix tree structure; Adders; CMOS integrated circuits; Delays; Hybrid power systems; Layout; Logic gates; Low voltage; carry select adder; hybrid adder; low power; low voltage; prefix tree structure;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer, Consumer and Control (IS3C), 2014 International Symposium on

Conference_Location

Taichung

Type

conf

DOI

10.1109/IS3C.2014.123

Filename

6845915