Title :
Systolic circuits for fast transform algorithms
Author :
Marchesi, M. ; Orlandi, G. ; Piazza, E.
Author_Institution :
Dipartimento Elettronica ed Automatica, Ancona Univ., Italy
Abstract :
Fast algorithms for calculating the discrete Hartley transform and the Fermat number transform (FNT) are discussed from an architectural point of view. Several systolic architectures for the real-time computation of these transforms are presented. In particular, the cascade architecture for computing the FNT with the decimation-in-time algorithm is presented
Keywords :
cellular arrays; computerised signal processing; transforms; Fermat number transform; cascade architecture; computerised signal processing; decimation-in-time algorithm; discrete Hartley transform; fast transform algorithms; real-time computation; systolic architectures; Circuits; Computer architecture; Convolution; DH-HEMTs; Digital signal processors; Discrete Fourier transforms; Discrete transforms; Signal processing; Signal processing algorithms; Very large scale integration;
Conference_Titel :
Electrotechnical Conference, 1989. Proceedings. 'Integrating Research, Industry and Education in Energy and Communication Engineering', MELECON '89., Mediterranean
Conference_Location :
Lisbon
DOI :
10.1109/MELCON.1989.50042
