Title :
Adaptive-Bandwidth Mixing PLL/DLL Based Multi-Phase Clock Generator for Optimal Jitter Performance
Author :
Tan, Amber Han-Yuan ; Wei, Gu-Yeon
Author_Institution :
Div. of Eng. & Appl. Sci., Harvard Univ., Cambridge, MA
Abstract :
This paper presents an adaptive-bandwidth mixing PLL/DLL (MX-PDLL) based multi-phase clock generator that can operate as a PLL, DLL, or a mixture of the two. Moreover, this clock generator can be used in a proposed dual-loop CDR to minimize output clock jitter under various noise environments. A test-chip prototype of the MX-PDLL and a 360deg phase rotator was fabricated in a 0.18mum CMOS process, operating off of a 1.8V supply. Experimentally measured results verify that while PLL-mode operation offers the ability to better filter quantization noise from the digital CDR control, shifting towards DLL-mode operation offers the ability to reduce jitter as the amount of on-chip noise increases
Keywords :
CMOS integrated circuits; adaptive modulation; clocks; phase locked loops; timing jitter; 0.18 micron; 1.8 V; CMOS process; DLL; MX-PDLL; PLL; adaptive bandwidth mixing; clock jitter; digital CDR control; dual loop CDR; filter quantization noise; multi phase clock generator; optimal jitter performance; phase rotator; test chip prototype; CMOS process; Clocks; Jitter; Noise generators; Noise measurement; Noise reduction; Phase locked loops; Prototypes; Testing; Working environment noise;
Conference_Titel :
Custom Integrated Circuits Conference, 2006. CICC '06. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
1-4244-0075-9
Electronic_ISBN :
1-4244-0076-7
DOI :
10.1109/CICC.2006.320967
