Title :
A Low Jitter Multi-Phase PLL with Capacitive Coupling
Author :
Park, JunYoung ; Flynn, Michael P.
Author_Institution :
Michigan Univ., Ann Arbor, MI
Abstract :
Capacitive coupling improves both phase noise and phase accuracy in coupled LC oscillators since the coupling current is in phase with the regeneration current. A prototype 3 GHz PLL with four LC oscillator stages and capacitive coupling is fabricated in 0.13mum CMOS. The long term measured RMS jitter of the buffered clock from the PLL is 1.61ps and the pk-pk jitter is 13.33ps
Keywords :
CMOS integrated circuits; clocks; phase locked loops; phase noise; timing jitter; 0.13 micron; 1.61 ps; 13.33 ps; 3 GHz; CMOS; RMS jitter; buffered clock; capacitive coupling; coupled LC oscillators; low jitter multi-phase PLL; phase accuracy; phase noise; pk-pk jitter; regeneration current; Capacitors; Clocks; Coupling circuits; Injection-locked oscillators; Jitter; Phase locked loops; Phase noise; Prototypes; Radio frequency; Ring oscillators;
Conference_Titel :
Custom Integrated Circuits Conference, 2006. CICC '06. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
1-4244-0075-9
Electronic_ISBN :
1-4244-0076-7
DOI :
10.1109/CICC.2006.320968
